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FEATURES Li-Ion Battery Charger Three Battery Voltage Options Selectable 12.525 V/16.700 V Selectable 12.600 V/16.800 V Adjustable High End-of-Charge Voltage Accuracy 0.4% @ 25 C 0.6% @ 5 C to 55 C 0.7% @ 0 C to 85 C Programmable Charge Current with Rail-to-Rail Sensing System Current Sense with Reverse Input Protection Softstart Charge Current Undervoltage Lockout Bootstrapped Synchronous Drive for External NMOS Programmable Oscillator Frequency Oscillator SYNC Pin Low Current Flag Trickle Charge APPLICATIONS Portable Computers Fast Chargers
High-Frequency Switch Mode Li-Ion Battery Charger ADP3806
GENERAL DESCRIPTION
The ADP3806 is a complete Li-Ion battery-charging IC. The device combines high output voltage accuracy with constant current control to simplify the implementation of ConstantCurrent, Constant-Voltage (CCCV) chargers. The ADP3806 is available in three options. The ADP3806-12.6 guarantees the final battery voltage be selected to 12.6 V or 16.8 V 0.6%, the ADP3806-12.5 guarantees 12.525 V/16.7 V 0.6% and the ADP3806 is adjustable using two external resistors to set the battery voltage. The current sense amplifier has rail-to-rail inputs to accurately operate under low drop out and short circuit conditions. The charge current is programmable with a dc voltage on ISET. A second differential amplifier senses the system current across an external sense resistor and outputs a linear voltage on the ISYS pin. The bootstrapped synchronous driver allows the use of two NMOS transistors for lower system cost.
FUNCTIONAL BLOCK DIAGRAM
VCC BST DRVH SW DRVL PGND CS+ CS- SYS+ SYS- ISYS
BOOTSTRAPPED SYNCHRONOUS DRIVER SD VREF + VREG UVLO BIAS VREF IN DRVLSD DRVLSD + VTH -
+ - AMP1
- + AMP2 - LIMIT 2.5V +
BSTREG
- + -
SD
LOGIC CONTROL - gm2 + VREF SELECT 12.6/16.8
LC
OSCILLATOR
ADP3806
AGND
REG
REF
SYNC
CT
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
+
- gm1 +
ISET BAT
COMP
BATSEL
ADP3806-SPECIFICATIONS (@ 0 C T 100 C, VCC = 16 V, unless otherwise noted.)
A
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
BATTERY SENSE INPUT ADP3806-12.6 V and 16.8 V ADP3806-12.525 V and 16.7 V TA = 25C, 13 V VCC 5C TA 55C 0C TA 85C Part in Operation Part in Shutdown 20 V VBAT VBAT VBAT RBAT IBAT(SD) -0.4 -0.6 -0.7 250 +0.4 +0.6 +0.7 350 0.2 1.0 % % % k A
Input Resistance Input Current BATTERY SENSE INPUT ADP3806 VBAT = 2.5 V Input Current Operating Input Current Shutdown
TA = 25C, 13 V VCC 20 V 0C TA 85C BATSEL = Open, Part in Operation BATSEL = 100 k to GND, Part in Shutdown
VBAT VBAT
-0.5 -0.7 0.2 0.2
+0.5 +0.7 1.0 1.0
% % A A kHz kHz A V V V V A ns ns A V V mV mV V/V A A A mV V mV mV A A V/V V V V
OSCILLATOR Maximum Frequency2 Frequency Variation3 CT = 180 pF CT Charge Current 0% Duty Cycle Threshold @ COMP Pin Maximum Duty Cycle Threshold @ COMP Pin SYNC Input High SYNC Input Low SYNC Input Current GATE DRIVE On Resistance Rise, Fall Time Overlap Protection Delay SW Bias Current BST Cap Refresh Threshold CURRENT SENSE AMPLIFIER Input Common-Mode Range Input Differential Mode Range Input Offset Voltage5 Gain5 Input Bias Current Input Offset Current Input Bias Current DRVL Shutdown Threshold SYSTEM CURRENT SENSE Input Common-Mode Range Input Differential Range Input Offset Voltage Input Bias Current, SYS+ Input Bias Current, SYSVoltage Gain Output Range Limit Output Threshold Limit Output Voltage
6
fCT fCT ICT SYNCH SYNCL ISYNC RON t r , tf tOP
1000 210 125
250 150 1.0 2.5
290 175
2.2 0.2 6 35 50 0.2 3.7 0.8 1.0 10
IL = 10 mA CL = 1 nF, DRVL and DRVH DRVL Falling to DRVH Rising, DRVH Falling to DRVL Rising Part in Shutdown, VSW = 12.6 V VBST - VSW VCS+ and VCS- VCS4 0 V VCS(CM)
1.0
VCC
VCS(CM) VCS(DM) VCS(VOS) VCS(IB) VCS(IOS) VCS(SD) VSYS(CM) VSYS(DM) IB(SYS+) IB(SYS-)
0.0 0.0 1.0 25 50 1.0 0.2 48 4.0 0 0.5 200 70 50 2.5 0.1
VCC + 0.3 160
0 V VCS(CM) VCC, Part in Operation 0 V VCS(CM) VCC Part in Shutdown Measured between VCS+ and VCSSYS+ and SYS-, IL = 0 mA, VISYS = 3 V (VSYS+) - (VSYS-) VSYS(DM) = 0 V, VSYS(CM) = 16 V VSYS(DM) = 0 V, VSYS(CM) = 16 V 10 V VSYS(CM) VCC + 0.3 V, IL = 100 A IL = 1 mA7, VSYS(CM) > 6 V VLIMIT 0.2 V, 50 k Pull-up to 5 V VISYS > 2.65 V, ISINK = 700 A
100 2.0 1.0
VCC + 0.3 100 300 125 51.5 5.0 2.7 0.2
48.5 VISYS 0 VTH(LIMIT) 2.3 VO(LIMIT)
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ADP3806
Parameter Conditions Symbol Min Typ Max Unit ISET INPUT Charge Current Programming Function 0.0 V VISET 4.0 V Programming Function Accuracy VISET = 4.0 V, 1 V VCS(CM) 16V VISET = 0.50 V, 1 V VCS(CM) 10V ISET Bias Current 0.0 V VISET 4.0 V BATSEL INPUT VBAT = 12.6 V VBAT = 16.8 V BATSEL Input Current BOOST REGULATOR OUTPUT Output Voltage Output Current10 ANALOG REGULATOR OUTPUT Output Voltage Output Current10 PRECISION REFERENCE OUTPUT Output Voltage Output Current10 SHUTDOWN (SD) ON OFF SD Input Current POWER SUPPLY ON Supply Current OFF Supply Current UVLO Threshold Voltage UVLO Hysteresis LC OUTPUT Output Voltage Low Output Voltage High OUTPUT REVERSE LEAKAGE PROTECTION Leakage Current OVERCURRENT COMPARATOR Overcurrent Threshold Response Time No External Loads, UVLO VCC No External Loads, VCC 20 V Turn On Turn Off High Current Mode8, ISINK = 100 A Low Current Mode9 20 V
VISET/VCS -5 -30 IB 2.0
25 1.0 10 0.2
+5 +30 1.0
V/V % % A V V
0.2
0.8 5.0
CL = 0.1 F
VBSTREG IBSTREG
6.8 3.0
7.0 5.0
7.2
V mA
CL = 10 nF
VREG IREG
5.8 3.0
6.0 5.0
6.2
V mA
VREF IREF SDH SDL
2.47 0.5 2.0
2.5 1.1
2.53
V mA V V A mA A V V V V
0.2 ISYON ISYOFF VUVLO 6.0 1.0 6.0 0.3
0.8 1.0 8.0 5.0 6.25 0.5
5.65 0.1
0.1 0.4 External
VCC = Floating, VBAT = 12.6 V
IDISCH
1
5
A
VCS > 180 mV to COMP < 1 V
VCS(OC) tOC VBAT(OV) tOV
180 2 120 2
mV s % s
OVERVOLTAGE COMPARATOR Overvoltage Threshold Response Time VBAT > 120% to COMP < 1 V
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by design, not tested in production. 3 If SYNC function is used, then f SYNC must be greater than fCT, but less than 120% of f CT. 4 VCS = (VCS+) - (VCS-). 5 Accuracy guaranteed by ISET INPUT, Programming Function Accuracy specification. 6 System current sense is active during shutdown. 7 Load current is supplied through SYS+ pin. 8 VBAT 93% of final or V CS 25 mV. 9 VBAT 93% of final and V CS 25 mV. 10 Guaranteed Output Current from 0 to Min specified value to maintain regulation. Specifications subject to change without notice.
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ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS
Input Voltage (VCC) . . . . . . . . . . . . . . . . . . . -0.3 V to +25 V BAT, CS+, CS- . . . . . . . . . . . . . . . . . . -0.3 V to VCC +0.3 V SYS+, SYS- . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 V to +25 V BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -4 V to +25 V DRVL to PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +8 V ISET, BATSEL, SD, SYNC, CT, LIMIT, ISYS, LC . . . . . . . . . . . . . . . . . . . . -0.3 V to +10 V COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +3 V GND to PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Operating Ambient Temperature Range . . . . . . 0C to 100C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C/W Operating Junction Temperature Range . . . . . . 0C to 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C
*This is a stress rating only, operation these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Mnemonic VCC SYS- SYS+ ISYS LIMIT CT SYNC REG REF SD COMP LC AGND BAT
Function Supply Voltage Negative System Current Sense Input Positive System Current Sense Input System Current Sense Output System Current Sense Limit Output Oscillator Timing Capacitor Oscillator Synchronization Pin 6.0 V Analog Regulator Output 2.5 V Precision Reference Output Shutdown Control Input External Compensation Node Low Current Output Analog Ground Battery Sense Input. 2.5 V for ADP3806, 12.525 V/16.7 V for ADP3806-12.5, or 12.6 V/16.8 V for ADP3806-12.6 Battery Voltage Sense Input High = 3 Cells, Low = 4 Cells Charge Current Program Input Negative Current Sense Input Positive Current Sense Input Power Ground Low Drive Output switches between REG and PGND 7.0 V Regulator Output for Boost Floating Bootstrap Supply for DRVH High Drive Output switches between SW and BST Buck Switching Node Reference for DRVH
ORDERING GUIDE
Model ADP3806JRU ADP3806JRU-12.5 ADP3806JRU-12.6
Battery Voltage Adjustable 12.525 V/ 16.7 V 12.600 V/ 16.8 V
Package Description TSSOP-24 TSSOP-24 TSSOP-24
Package Option RU-24 RU-24 RU-24
15 16 17 18 19 20 21 22 23 24
BATSEL ISET CS- CS+ PGND DRVL BSTREG BST DRVH SW
PIN CONFIGURATION
24-Lead TSSOP
VCC 1 SYS- 2 SYS+ 3 ISYS 4 LIMIT 5 CT 6
24 SW 23 DRVH 22 BST 21 BSTREG
ADP3806
20 DRVL
TOP VIEW 19 PGND SYNC 7 (Not to Scale) 18 CS+ REG 8 REF 9 SD 10 COMP 11 LC 12
17 CS- 16 ISET 15 BATSEL 14 BAT 13 AGND
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3806 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Typical Performance Characteristics-ADP3806
30 VCC = 16V TA = 25 C 25
0.5 0.4 0.3
VREF ACCURACY - %
VCC = 16V
NUMBER OF PARTS
20
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
15
10
5
0 -0.5
-0.5
-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
0
20
VBAT ACCURACY - %
40 60 TEMPERATURE - C
80
100
TPC 1. VBAT Accuracy Distribution
TPC 4. VREF Accuracy vs. Temperature
0.4 VCC = 16V 0.3 0.2
VBAT ACCURACY - %
0.10 TA = 25 C 0.08 0.06 VREF ACCURACY - % 0.04 0.02 0 -0.02 -0.04 -0.06
0.1 0 -0.1 -0.2 -0.3 -0.4 0 20 40 60 TEMPERATURE - C 80 100
-0.08 -0.10 5 10 VCC - V 15 20
TPC 2. VBAT Accuracy vs. Temperature
TPC 5. VREF Accuracy vs. VCC
0.10 TA = 25 C
ON SUPPLY CURRENT - mA
6.0 NO LOADS 5.6
0.05
VBAT ACCURACY - %
5.2 TA = 100 C 4.8 TA = 0 C
0
TA = 25 C
-0.05
4.4
-0.10 10
4.0
12
14 VCC - V
16
18
20
10
12
14 VCC - V
16
18
20
TPC 3. VBAT Accuracy vs. Supply Voltage
TPC 6. ON Supply Current vs. VCC
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ADP3806
18 16 14
SUPPLY CURRENT - mA
6 VCC = 16V TA = 25 C fOSC = 250kHz VCC = 16V TA = 25 C
5
50k
TO 5V
12 10 8 6 4
VLIMIT - Volts
4
3 50k 2 TO 2.5V
1 2 0 0 500 1000 1500 2000 2500 DRIVER LOAD CAPACITANCE - pF 3000 3500 0 2.0
2.2
2.4
2.6 VISYS - V
2.8
3.0
3.2
TPC 7. Supply Current vs. Driver Load Capacitance
TPC 10. VLIMIT vs. VISYS
1.0
10 VCC = 16V
OFF SUPPLY CURRENT - A
0.8 TA = 100 C 0.6
8
DRIVER ON RESISTANCE -
DRIVER SOURCING 6 DRIVER SINKING 4
0.4 TA = 25 C 0.2 TA = 0 C
2
0 10.0
0 12.5 15.0 VCC - V 17.5 20.0 0 20 40 60 TEMPERATURE - C 80 100
TPC 8. OFF Supply Current vs. VCC
TPC 11. Driver On-Resistance vs. Temperature
600 VCC = 16V TA = 25 C 500
DRVH 5V/DIV VCC = 16V TA = 25 C FIGURE 1
FREQUENCY - kHz
400
300
DRVL 5V/DIV
200
100
200ns/DIV
0 0 200 400 CT - pF 600 800
TPC 9. Oscillator Frequency vs. CT
TPC 12. Driver Waveforms
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ADP3806
100 98 1.00
CONVERSION EFFICIENCY - %
96 94 92 90 88 86 84 82 80 0.1 VCC = 19V VBAT = 12.4V TA = 25 C FIGURE 1 EFFICIENCY
0.95 19VIN 0 C
0.90
0.85 19VIN 85 C 0.80
0.75
0.70 1 CHARGE CURRENT - Amps 10 2 4 6 8 VO 10 12 14
TPC 13. Conversion Efficiency vs. Charge Current
TPC 15. Conversion Efficiency vs. Battery Voltage at Temperatures
96 ICHARGE = 2A ICHARGE = 3A
94
CONVERSION EFFICIENCY - %
92
90
88
86 VCC = 19V TA = 25 C FIGURE 1 3 4 5 6 7 8 VBAT - V 9 10 11 12 13
84
82
TPC 14. Conversion Efficiency vs. Battery Voltage
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ADP3806
THEORY OF OPERATION
The ADP3806 combines a bootstrapped synchronous switching driver with programmable current control and accurate final battery voltage control in a Constant Current, Constant Voltage (CCCV) Li-Ion battery charger. High accuracy voltage control is needed to safely charge Li-Ion batteries, which are typically specified at 4.2 V 1% per cell. For a typical notebook computer battery pack, three or four cells are in series giving a total voltage of 12.6 V or 16.8 V. The ADP3806 is available in three versions, a selectable 12.525 V/16.7 V output, a selectable 12.6 V/16.8 V output, and an adjustable output. The adjustable output can be programmed for a wide range of battery voltages using two external precision resistors. Another requirement for safely charging Li-Ion batteries is accurate control of the charge current. The actual charge current depends on the number of cells in parallel within the battery pack. Typically this is in the range of 2 A to 3 A. The ADP3806 provides flexibility in programming the charge current over a wide range. An external resistor is used to sense the charge current and this voltage is compared to a DC input voltage. This programmability allows the current to be changed during charging. For example, the charge current can be reduced for trickle charging.
The synchronous driver provides high efficiency when charging at high currents. Efficiency is important mainly to reduce the amount of heat generated in the charger, but also to stay within the power limits of the AC adapter. With the addition of a bootstrapped high side driver, the ADP3806 drives two external power NMOS transistors for a simple, lower cost power stage. The ADP3806 also provides an uncommitted current sense amplifier. This amplifier provides an analog output pin for monitoring the current through an external sense resistor. The amplifier can be used anywhere in the system that high side current sensing is needed.
Charge Current Control
AMP1 in Figure 1 has a differential input to amplify the voltage drop across an external sense resistor RCS. The input common mode range is from ground to VCC allowing current control in short circuit and low drop-out conditions. The gain of AMP1 is internally set to 25 V/V for low voltage drop across the sense resistor. During CC mode, gm1 forces the voltage at the output of AMP1 to be equal to the external voltage at the ISET pin. By choosing RCS and VISET appropriately, a wide range of charge currents can be programmed:
I CHARGE = VISET 25 x RCS
RSS 10m
(1)
1/2 Q1 FD56990A VIN R13 10 C14 2.2 F C15 + 22 F - C9 100nF DRVH 1/2 Q1 FD56990A
L1 22 H C16 + 22 F -
RCS 40m R3 249 C13 22nF R4 249 C1 470nF SYS+ SYS- R1 2.2 R2 2.2 C2 470nF ISYS
SYSTEM DC/DC
BATTERY 12.6V/16.8V
VCC
BST
SW
DRVL
PGND
CS+
CS-
AMP1 DRVLSD - + VTH - gm1 +
AMP2 - LIMIT + 2.5V ISET *R11 412k 0.1%
SD VREF + VREG UVLO BIAS VREF
IN DRVLSD
BSTREG 7.0V C10 0.1 F SD
+ - LOGIC CONTROL
LC OSCILLATOR **R7 100k
- gm2 + VREF
ADP3806
AGND
REG 6.0V
REF 2.5V
SYNC
CT
COMP C8 0.22 F R8 56
C7 200pF C17 100nF
C6 180pF
*R12 102k 0.1%
*ADP3806-12.6, ADP3806-12.5: R11 = SHORT, R12 = OPEN; ADP3806, R11 = 412k , R12 = 102k , R14 = OPEN. **R7, OPEN IF LC FUNCTION IS NOT USED.
Figure 1. Typical Application
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+ BAT SELECT 12.6/16.8 BATSEL *R14 0 R5 6.81k R6 7.5k
-
-
+
BOOTSTRAPPED SYNCHRONOUS DRIVER
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ADP3806
Typical values of RCS are in the range from 25 m to 50 m, and the input range of ISET is from 0 V to 4 V. If, for example, a 3 A charger is required, RCS could be set to 40 m and VISET = 3 V. The power dissipation in RCS should be kept below 500 mW. In this example, the power is a maximum of 360 mW. Once RCS has been chosen, the charge current can be adjusted during operation with VISET. Lowering VISET to 125 mV gives a charge current of 125 mA for trickle charging. Components R3, R4, and C13 provide high-frequency filtering for the current sense signal.
Final Battery Voltage Control
In contrast, the ADP3806 requires external, precision resistors. The divider ratio should be set to divide the desired final voltage down to 2.5 V at the BAT pin:
R11 VBATTERY = -1 R12 2.5 V
(2)
As the battery approaches its final voltage, the ADP3806 switches from CC mode to CV mode. The change is achieved by the common output node of gm1 and gm2. Only one of the two outputs controls the voltage at the COMP pin. Both amplifiers can only pull down on COMP, such that when either amplifier has a positive differential input voltage, its output is not active. For example, when the battery voltage, VBAT, is low, gm2 does not control VCOMP. When the battery voltage reaches the desired final voltage, gm2 takes control of the loop, and the charge current is reduced. Amplifier gm2 compares the battery voltage to the internal reference voltage of 2.5 V. In the case of the ADP3806-12.5 and ADP3806-12.6, an internal resistor divider sets the selectable final battery voltage. When BATSEL is high, the final battery voltage is set to three cells (12.6 V or 12.525 V). BATSEL can be tied to REG for this state. When BATSEL is tied to ground, VBAT equals four cells (16.8 V or 16.7 V). BATSEL has a 2 pull-up current as a fail-safe to select three cells when it is left open. The reference and internal resistor divider are referenced to the AGND pin, which should be connected close to the negative terminal of the battery to minimize sensing errors.
These resistors should have a parallel impedance of approximately 80 k to minimize bias current errors. When the ADP3806 is in shutdown, an internal switch disconnects the BAT pin as shown in Figure 2. This disconnects the resistor, R11 from the battery and minimizes leakage. The resistance of the internal switch is less than 200 .
ADP3806
SD BAT R11 412k 0.1% BATTERY
gm2 VREF BATSEL R12 102k 0.1%
Figure 2. Battery Sense Disconnect Circuit
Oscillator and PWM
The oscillator generates a triangle waveform between 1 V and 2.5 V, which is compared to the voltage at the COMP pin, setting the duty cycle of the driver stage. When VCOMP is below 1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches its maximum.
BSTREG
ADP3806
BOOTSTRAPPED SYNCHRONOUS DRIVER BST CMP3 CBST IN MIN OFF TIME + SD - SW - CMP2 + 1V DRVH
Q1
DELAY
- CMP1 + 1V DELAY
DRVL PGND
Q2
DRVLSD
Figure 3. Bootstrapped Synchronous Driver
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ADP3806
The oscillator frequency is set by the external capacitor at the CT pin and the internal current source of 150 A according to the following formula:
fOSC = 150 A 2 .2 x CT x 1 .5 V
(3)
The driver stage monitors the voltage across the BST cap with CMP3. When this voltage is less than 4 V, CMP3 forces a minimum offtime of 200 ns. This ensures that the BST cap is charged even during DRVLSD. However, because a minimum off time is only forced when needed, the maximum duty cycle is greater than 99%.
2.5 V Precision Reference
A 180 pF capacitor sets the frequency to 250 kHz. The frequency can also be synchronized to an external oscillator by applying a square wave input on SYNC. The SYNC function is designed to allow only increases in the oscillator frequency. The fSYNC should be no more than 20% higher than fOSC. The duty cycle of the SYNC input is not important and can be anywhere between 5% and 95%.
7 V Bootstrap Regulator
The voltage at the BAT pin is compared to an internal precision, low temperature drift reference of 2.5 V. The reference is available externally at the REF pin. This pin should be bypassed with a 100 pF capacitor to the analog ground pin, AGND. The reference can be used as a precision voltage externally. However, the current draw should not be greater than 100 A, and noisy, switching type loads should not be connected.
6 V Regulator
The driver stage is powered by the internal 7 V bootstrap regulator, which is available at the BSTREG pin. Because the switching currents are supplied by this regulator, decoupling must be added. A 0.1 F capacitor should be placed close to the ADP3806, with the ground side connected close to the power ground pin, PGND. This supply is not recommended for use externally due to high switching noise.
Bootstrapped Synchronous Driver
The 6 V regulator supplies power to most of the analog circuitry on the ADP3806. This regulator should be bypassed to AGND with a 0.1 F capacitor. This reference has a 3 mA source capability to power external loads if needed.
LC
The PWM comparator controls the state of the synchronous driver shown in Figure 3. A high output from the PWM comparator forces DRVH on and DRVL off. The drivers have an ON resistance of approximately 6 for fast rise and fall times when driving external MOSFETs. Furthermore, the bootstrapped drive allows an external NMOS transistor for the main switch instead of a PMOS. An external boost diode should be connected between BSTREG and BST, and a boost capacitor of 0.1 F must be added externally between BST and SW. The voltage between BST and SW is typically 6.5 V. The DRVL pin switches between BSTREG and PGND. The 7 V output of BSTREG drives the external NMOS with high VGS to lower the ON resistance. PGND should be connected close to the source pin of the external synchronous NMOS. When DRVL is high, this turns on the lower NMOS and pulls the SW node to ground. At this point, the boost capacitor is charged up through the boost diode. When the PWM switches high, DRVL is turned off and DRVH turns on. DRVH switches between BST and SW. When DRVH is on, the SW pin is pulled up to the input supply (typically 16 V), and BST rises above this voltage by approximately 6.5 V. Overlap protection is included in the driver to ensure that both external MOSFETs are not on at the same time. When DRVH turns off the upper MOSFET, the SW node goes low due to the inductor current. The ADP3806 monitors the SW voltage, and DRVL goes high to turn on the lower MOSFET when SW goes below 1 V. When DRVL turns off, an internal timer adds a delay of 50 ns before turning DRVH on. When the charge current is low, the DRVLSD comparator signals the driver to turn off the low side MOSFET and DRVL is held low. As shown in Figure 1, the DRVLSD comparator looks at the output of AMP1. The DRVLSD threshold is set to 1.2 V, corresponding to 48 mV differential voltage between the CS pins.
The ADP3806 provides a low current (LC) logic output to signal when the current sense voltage (VCS) is below a fixed threshold and the battery voltage is greater than 95%. LC is an open drain output that is pulled low when VCS is above the threshold. When the low current threshold condition is reached, LC is pulled high by an external resistor to REF or another appropriate pull-up voltage. To determine when LC goes low, an internal comparator senses when the current falls below 12.5% of full scale (20 mV across the CS pins). The comparator has hysteresis to prevent oscillation around the trip point. To prevent false triggering (such as during soft-start), the comparator is only enabled when the battery voltage is within 5% of its final voltage. As the battery is charging up, the comparator will not go low even if the current falls below 12.5% as long as the battery voltage is below 95% of full scale. Once the battery has risen above 95%, the comparator is enabled. This pin can be used to indicate the end of the charge process.
System Current Sense
An uncommitted differential amplifier is provided for additional high side current sensing. This amplifier, AMP2, has a fixed gain of 50 V/V from the SYS+ and SYS- pins to the analog output at ISYS. ISYS has a 1 mA source capability to drive an external load. The common-mode range of the input pins is from 4 V to VCC. This amplifier is the only part of the ADP3806 that remains active during shutdown. The power to this block is derived from the bias current on the SYS+ and SYS- pins. A separate comparator at the LIMIT pin signals when the voltage on the ISYS pin exceeds 2.5 V typically. The internal comparator has an open drain output, which produces the function shown in the TPC 10 graph of V LIMIT versus V ISYS. The LIMIT pin should be externally pulled up to 5 V, 2.5 V, or other voltage as needed through a resistor. This graph was taken with a 50 k pull-up resistor to 5 V and to 2.5 V. When ISYS is below 2.4 V, the LIMIT pin has high output impedance. The open drain output is capable of sinking 700 A when the threshold is exceeded. This comparator is turned off during shutdown to conserve power.
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ADP3806
Shutdown
A high impedance CMOS logic input is provided to turn off the ADP3806. When the voltage on SD is less than 0.8 V, the ADP3806 is placed in low power shutdown. With the exception of the system current sense amplifier, AMP2, all other circuitry is turned off. The reference and regulators are pulled to ground during shutdown and all switching is stopped. During this state, the supply current is less than 5 A. Also, the BAT, CS+, CS-, and SW pins go to high impedance to minimize current drain from the battery.
UVLO
APPLICATION INFORMATION Design Procedure
Please refer to Figure 1, the typical application circuit, for the following description. The design follows that of a buck converter. With Li-Ion cells it is important to have a regulator with accurate output voltage control.
Battery Voltage Settings: The ADP3806 has three options for voltage selection:
1. 12.525 V/16.7 V as selectable fixed voltages. 2. 12.6 V/16.8 V as selectable fixed voltages. 3. Adjustable. When using the fixed versions, R11 should be a short or 0 wire jumper and R12 should be an open circuit. When using the adjustable version, the following equation gives the ratio of the two resistors: R11 VBAT = -1 R12 2.5 (5)
Under-Voltage Lock-Out, UVLO, is included in the ADP3806 to ensure proper start-up. As VCC rises above 1 V, the reference and regulators will track VCC until they reach their final voltages. However, the rest of the circuitry is held off by the UVLO comparator. The UVLO comparator monitors both regulators to ensure that they are above 5 V before turning on the main charger circuitry. This occurs when VCC reaches 6 V. Monitoring the regulator outputs makes sure that the charger circuitry and driver stage have sufficient voltage to operate normally. The UVLO comparator includes 300 mV of hysteresis to prevent oscillations near the threshold.
Startup Sequence
Often 0.1% resistors are required to maintain the overall accuracy budget in the design. Inductor Selection: Usually the inductor is chosen based on the assumption that the inductor ripple current is 15% of the maximum output dc current at maximum input voltage. As long as the inductor used has a value close to this, the system should work fine. The final choice affects the trade-offs between cost, size, and efficiency. For example, the lower the inductance, the size is smaller but ripple current is higher. This situation, if taken too far, will lead to higher ac losses in the core and the windings. Conversely, a higher inductance results in lower ripple current and smaller output filter capacitors, but the transient response will be slower. With these considerations the required inductance can be found from:
L1 = VIN , MAX - VBAT x DMIN x TS I
During a startup from either SD going high or VCC exceeding the UVLO threshold, the ADP3806 initiates a soft-start sequence. The soft-start timing is set by the compensation capacitor at the COMP pin and an internal 40 A source. Initially, both DRVH and DRVL are held low until VCOMP reaches 1 V. This delay time is set by:
t DELAY =
CCOMP x 1V 40 A
(4)
For a 0.22 F COMP capacitor, tDELAY is 5 ms. After this initial delay, the duty cycle is very low and then ramps up to its final value with the same ramp rate given for tDELAY. For example, if VIN is 16 V and the battery is 10 V when charging is started, the duty cycle will be approximately 65%, corresponding to a VCOMP of ~2 V. The time for the duty cycle to ramp from 0% at VCOMP = 1 V to 65% at VCOMP = 2 V is approximately 5 ms. Because the charge current is equal to zero at first, DRVLSD is active and DRVL will not turn on. However, if the BST cap is discharged, DRVL will be forced on for a minimum ON time of 200 ns each clock period until the BST cap is charged to greater than 4 V. Typically the BST cap is charged in 5 to 10 clock cycles.
Loop Feed Forward
(6)
where the maximum input voltage VIN, MAX is used with the minimum duty ratio DMIN. The duty ratio is defined as the ratio of the output voltage to the input voltage, VBAT/VIN. The ripple current is found from:
I = 0.3 x I BAT , MAX
(7)
the maximum peak-to-peak ripple is 30%, that is 0.3, and maximum battery current, IBAT, MAX is used. For example, with VIN, MAX = 19 V, VBAT = 12.6 V, IBAT, MAX = 3A, and TS = 4 s, the value of L1 is calculated as 18.9 H. Choosing the closest standard value gives L1 = 22 H. Output Capacitor Selection: An output capacitor is needed in the charger circuit to absorb the switching frequency ripple current and smooth the output voltage. The RMS value of the output ripple current is given by:
As the startup sequence discussion shows, the response time at COMP is slowed by the large compensation capacitor. To speed up the response, two comparators can quickly feed forward around the normal control loop and pull the COMP node down to limit any over shoot in either short circuit or overvoltage conditions. The overvoltage comparator has a trip point set to 20% higher than the final battery voltage. The overcurrent comparator threshold is set to 180 mV across the CS pins, which is 15% above the maximum programmable threshold. When these comparators are tripped, a normal soft-start sequence is initiated. The overvoltage comparator is valuable when the battery is removed during charging. In this case, the current in the inductor causes the output voltage to spike up, and the comparator limits the maximum voltage. Neither of these comparators affect the loop under normal charging conditions. REV. 0
I RMS =
VIN , MAX fL1 12
D(1 - D)
(8)
The maximum value occurs when the duty cycle is 0.5. Thus:
I RMS _ MAX = 0.072
-11-
VIN , MAX fL1
(9)
ADP3806
For an input voltage of 19 V and a 22 H inductance, the maximum RMS current is 0.26A. A typical 10 F or 22 F ceramic capacitor is a good choice to absorb this current. Input Capacitor Ripple: As is the case with a normal buck converter, the pulse current at the input has a high rms component. Therefore, since the input capacitor has to absorb this current ripple, it must have an appropriate rms current rating. The maximum input rms current is given by: MOSFET Selection: One of the features of the ADP3806 is that it allows use of a high-side NMOS switch instead of a more costly PMOS device. The converter also uses synchronous rectification for optimal efficiency. In order to use a high-side NMOS, an internal bootstrap regulator automatically generates a 7 V supply across C9.
C02611-1-10/01(0) PRINTED IN U.S.A.
0.028 (0.70) 0.020 (0.50)
I RMS =
PBAT x x D x VIN
D(1- D ) D
(10)
Maximum output current determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3806 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the load current. The power dissipation for each MOSFET is given by: Upper MOS
PDISS = RDS(ON) x (IBAT x D )2 +VIN x IBAT x D x TSW x f
where is the estimated converter efficiency (approximately 90%, 0.9) and PBAT is the maximum battery power consumed. This is a worst-case calculation and, depending on total charge time, the calculated number could be relaxed. Consult the capacitor manufacturer for further technical information. Decoupling the VCC Pin: It is a good idea to use an RC filter (R13 and C14) from the input voltage to the IC both to filter out switching noise and to supply bypass to the chip. During layout, this capacitor should be placed as close to the IC as possible. Values between 0.1 F and 2.2 F are recommended. Current-Sense Filtering: During normal circuit operation the current-sense signals can have high-frequency transients that need filtering to ensure proper operation. In the case of the CS+ and CS- inputs, the resistors (R3 and R4) are set to 249 while the filter capacitor (C13) value is 22 nF. For the system current sense circuits, common mode filtering from SYS+ and SYS- to ground is needed. 470 nF ceramic capacitors (C1, C2) with 2.2 resistors (R1, R2) will often due. These time constants can be adjusted in the laboratory if required, but represent a good starting point.
(11)
Lower MOS
PDISS = RDS(ON) x (IBAT x 1-D )2 +VIN x IBAT x 1-D x TSW x f (12)
Where f is the switching frequency and TSW is the switch transition time, usually 10 ns. The first term accounts for conduction losses while the second term estimates switching losses. Using these equations and the manufacturer's data sheets, the proper device can be selected. A Schottky diode D1 in parallel with Q2 conducts only during dead time between the two power MOSFETs. D1's purpose is to prevent the body-diode of the lower N-channel MOSFET from turning on which could cost as much as 1% in efficiency. One option is to use a combined MOSFET with the Schottky diode in a single package-these integrated packages often work better in practice. Examples are the IRF7807D2 and the Si4832.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Thin Shrink SO Package (TSSOP) (RU-24)
0.311 (7.90) 0.303 (7.70)
24
13
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 12
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
-12-
REV. 0

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